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Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
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New Allegro 16.5 Technology: The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB
designers benefits such as: - Higher functional density with a constraint-driven flow for embedded components - Faster timing closure with new PCB interconnect design planning technology - Fewer physical prototype iterations with concurrent team design authoring - More efficient low-power design with integrated power delivery network analysis - A compliant and faster implementation path with package/board-aware SoC IP - Smoother collaboration among global teams with new SiP distributed co-design - Flexibility through “base plus options†configurations
Fixed in Cadence SPB OrCAD 16.5.009: DATE: 10-26-2011 HOTFIX VERSION: 009
CCRID PRODUCT PRODUCTLEVEL2 TITLE
945 788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet 945 789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference DATE: 10-21-2011 HOTFIX VERSION: 008
CCRID PRODUCT PRODUCTLEVEL2 TITLE
906 827 ALLEGRO_EDITOR DATABASE Logic> Parts logic does not work correctly. 923 346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5 926 347 ADW COMPONENT_BROWSE Usability-Libflow Part check in comment should end up in Comments attribute for UCB / Designer to see it 929 348 007 F2B BOM Warning: Invalid output file path name 929 777 CONCEPT_HDL OTHER Component Revision Manager gives internal error 930 783 CONCEPT_HDL CORE Painting with groups with default colors 936 748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode. 938 143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR 938 281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V-V + pins 938 812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason. 939 075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window 939 193 F2B PACKAGERXL ERROR (SPCODD-439): Connectivity server is unable to load the design. 939 199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO) 939 346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set. 939 901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows "?" On lower hierarchy level nets after Upreving to 16.5 version. 939 918 PSPICE PROBE Print> Preview for output file causes Pspice crash. 940 217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part' 940 835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost 941 125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks 941 876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3 942 210 SCM OTHER Is the Project File argument is being correctly passed? 942 274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache 942 839 ALLEGRO_EDITOR GRAPHICS Graphics Issue-Pads are not visible 943 055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash DATE: 10-07-2011 HOTFIX VERSION: 007
CCRID PRODUCT PRODUCTLEVEL2 TITLE
841 096 APD WIREBOND Function required which to check wire not in die pad center. 903 263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits. 906 692 ADW LRM LRM window is always in front when opening a project 912 942 APD WIREBOND constraint driven wire bonding 912 951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems 915 178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design 917 887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors 923 315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure 927 382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license 927 664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp 930 152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one 930 180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation 930 188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked. 930 541 CAPTURE NETGROUPS NETGROUP element renaming doesn 'renames the associated net? 930 866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license. 930 926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form 931 274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC. 932 091 CONCEPT_HDL CORE Prop attached to SIG_NAME property 932 255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear 932 292 ADW LRM LRM crashes during Update operation on a customer design 932 639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns. 932 704 APD DEGASSING Shape> Degass never finishes on large GND plane 932 871 APD GRAPHICS could not see cursor as infinite 932 882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05 932 969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165> hotfix # 05 933 024 CAPTURE NETGROUPS Naming restrictions for NetGroup members 933 145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown 933 214 APD ARTWORK Film area report is larger when fillets are removed 933 356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop. 933 532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
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